1. Field of the Invention
The present invention relates to an improved substrate bias circuit having an insulated gate field-effect transistor (hereinafter referring to as MOS.multidot.FET) as the basic element such as a dynamic memory integrated circuit.
2. Description of the Prior Arts
In semiconductor integrated circuits having a MOS.multidot.FET as the main element, a signal is transmitted by charging and discharging the source region and the drain region of the MOS.multidot.FET. The operation of a MOS.multidot.FET-IC is faster depending upon the charging and discharging speed. For example, in a Random access memory (RAM), it is necessary to shorten the access time by reducing the charging or discharging speed. One of the main parameters effecting the charging and discharging speed is a junction capacitance based on the pn-junction between the semiconductor substrate and the source region and the drain region of the MOS.multidot.FET. The charging and discharging speed is increased to fasten the operation of MOS.multidot.FET-IC depending upon the decrease of the junction capacitance. The junction capacitance C.sub.J is given by the equation: ##EQU1## wherein the reference K designates a constant decided depending upon a semiconductor substrate and the configuration of the MOS.multidot.FET; V.sub.o designates a built-in potential which is usually about 0.6 V; and V designates a potential of the semiconductor substrate of the MOS.multidot.FET-IC based on the source region and the drain region of the MOS.multidot.FET (hereinafter referred to as potential difference).
When the potential difference V is a large negative value, the junction capacitance C.sub.J can be minimized as shown in the equation (I). In general, a voltage of 0 to +5 V is applied from a power source for the MOS.multidot.FET-IC to the source region and the drain region of MOS.multidot.FET. When the potential of the semiconductor substrate of the MOS.multidot.FET-IC is at ground potential, the potential difference V is in a range of 0 to +5 V. On the other hand, when a voltage of about -3 V is applied from the external power source to the semiconductor substrate of MOS.multidot.FET-IC, the potential difference V is in a range of -3 to -8 V. The junction capacitance C.sub.J is smaller than that when ground potential is applied to the semiconductor substrate of the MOS.multidot.FET-IC. Therefore, the faster operation of the MOS.multidot.FET-IC is attained. In order to avoid the need of an additional external power source, a substrate potential circuit device (substrate bias circuit) for generating a negative voltage is formed on the semiconductor substrate of MOS.multidot.FET-IC.
FIG. 1 is a partially enlarged sectional view of the conventional substrate bias circuit which relates to the present invention.
In FIG. 1, the reference numeral (1) designates a p-type substrate having an impurity concentration of 10.sup.14 /cm.sup.3 to 10.sup.15 /cm.sup.3 and having high specific resistance; (2), (3), (4), (5) and (6) respectively designate the first, second, third, fourth and fifth n.sup.+ -regions having lower resistance which has an impurity concentration of 10.sup.19 /cm.sup.3 ; (7) designates a first gate insulating thin layer made of silicon oxide, etc. which is formed from the first n.sup.+ -region (2) to the second n.sup.+ -region (3) on the main surface of the p-type substrate (1); (8) designates a second gate insulating thin layer made of silicon oxide, etc. which is formed from the third n.sup.+ -region (4) to the fourth n.sup.+ -region (5) on the main surface of the p-type substrate (1); (9) designates a third gate insulating thin layer made of silicon oxide, etc, which is formed from the fourth n.sup.+ -region (5) to the fifth n.sup.+ -region (6) on the main surface of the p-type substrate (1); (10) designates a first gate conductive layer made of polycrystalline silicon, aluminum or molybdenum which is formed on the first gate insulating layer (7); (11) designates a second gate conductive layer made of polycrystalline silicon, aluminum or molybdenum which is formed on the second gate insulating layer (8); (12) designates a third gate conductive layer made of polycrystalline silicon, aluminum, molybdenum etc., which is formed on the third gate insulating layer (9); (13) designates a n-reverse layer induced by the voltage applied to the first gate conductive layer (10) on the main surface under the first gate insulating layer (7); (14) designates a MOS capacitor comprising the first n.sup.+ -region (2), the second n.sup.+ -region (3) and the first gate conductive layer (10); (15) designates the first MOS.multidot.FET which comprises the third n.sup.+ -region as the source; the fourth n.sup.+ -region (5) as the drain; and the second gate conductive layer (11) as the gate; (16) designates the second MOS.multidot.FET which comprises the fourth n.sup.+ -region as the source; the fifth n.sup.+ -region as the drain; and the third gate conductor (12) as the gate; (17), (18), (19), (20) and (21) respectively designate the first, second, third, fourth and fifth electrodes which are respectively lead out from the first n.sup.+ -region (2), the second n.sup.+ -region (3), the third n.sup.+ -region (4), the fourth n.sup.+ -region (5) and the fifth n.sup.+ -region (6); (22) designates a sixth electrode lead out from the second main surface of the p-type substrate; (23), (24) and (25) respectively designate the first, second and third gate electrodes which are respectively lead out from the first gate conductive layer (10), the second gate conductive layer (11) and the third gate conductive layer (12); (26) designates a first wiring line for connecting the first electrode (17) to the second electrode (18); (27) designates a second wiring line for connecting the second electrode (18) to the second gate electrode (24) and the fourth electrode (20); (28) designates a third wiring line for connecting the third gate electrode (25) to the fifth electrode (21) and the sixth electrode (22). A known oscillation circuit having a known ring oscillation circuit (not shown) is formed on the first main surface of the p-type substrate (1) so as to apply the output signal of the circuit to the first gate electrode (23) of the MOS capacitor.
The operation of the conventional substrate bias circuit will be illustrated.
FIG. 2 is a circuit diagram of an equivalent circuit for illustrating the operation of the conventional substrate bias circuit.
In FIG. 2, the reference (29) designates a first parasitic diode having pn.sup.+ -junction formed between the first n.sup.+ -region (2) the second n.sup.+ -region (3) and the p-type substrate (1); (30) designates a second parasitic diode having pn.sup.+ -junction formed between the fourth n.sup.+ -region (5), and the p-type substrate (1); (31) designates a first parasitic capacitance which formed equivalently between the first n.sup.+ -region (2), the second n.sup.+ -type region (3); the fourth n.sup.+ -region (5) and the ground potential element; (32) designates a second parasitic capacitance formed equivalently between the p-type substrate (1) and the ground potential element.
FIG. 3(a) is an output signal of the conventional oscillation circuit. In this embodiment, the amplitude of the output voltage of the oscillation circuit is the same as the power voltage V.sub.DD. In the other cases, the same consideration can be applied.
When the signal shown in FIG. 3(a) is applied to the first gate electrode (23) of MOS capacaitor (14), the following amplitude V.sub.P of the potential of the first wiring line (26) and the second wiring line (27) are given by the capacitance coupling of the MOS capacitor (14). ##EQU2## wherein C.sub.14 designates a capacitance of the MOS capacity (14); C.sub.31 designates a capacitance of the first parasitic capacitance (31).
Usually C.sub.14 &gt;&gt;C.sub.31 and accordingly, the equation (II) approaches to the equation: EQU V.sub.P .apprxeq.V.sub.DD (III)
Usually, the potential of the third electrode (19) as the source electrode of the first MOS.multidot.FET (15) is ground potential, and accordingly, the first MOS.multidot.FED (15) is switched in the ON state when the potential of the second wiring line (27) reaches about the threshold voltage V.sub.T15 of the first MOS.multidot.FET (15). Thus, the potential of the second wiring line (27) is the value between the threshold voltage V.sub.T15 and -[V.sub.P -V.sub.T15 ].apprxeq.-[V.sub.DD -V.sub.T15 ] as shown in FIG. 3(b).
The case approaching to the normal state will be considered.
When the potential of the second wiring line (27) is about threshold voltage V.sub.T15, the second MOS.multidot.FET (16) and the first and second parasitic diode (29), (30) are in the OFF state whereas when it is -[V.sub.DD -V.sub.T15 ], the second MOS.multidot.FET (16) and the first and second parasitic diodes (29), (30) are in the ON state whereby the charge of the second parasitic capacitance (32) is discharged from the first gate electrode (23) through the second MOS.multidot.FET (16), the first and second parasitic diodes (29), (30) and the MOS capacitor (14).
In this discharge, the substrate potential of the p-type substrate (1) is given as one of the following equations depending upon values of V.sub.T16, V.sub.F29 and V.sub.F30. EQU -[V.sub.DD -V.sub.T15 -V.sub.T16 ] (IV) EQU -[V.sub.DD -V.sub.T15 -V.sub.F29 ] (V) EQU -[V.sub.DD -V.sub.T15 -V.sub.F30 ] (VI)
wherein V.sub.T16 designates a threshold voltage of the second MOS.multidot.FET (16); V.sub.F29 designates forward voltage drop of the first parasitic diode (29) and V.sub.F30 designates a forward voltage drop of the second parasitic diode (30).
FIG. 4 shows average discharged current of the second parasitic capacitance (32) in the case of V.sub.T16 &gt;V.sub.F29 +V.sub.F30.
The full line (a) shows the current component discharging from the second parasitic capacitance (32) through the first and second parasitic diodes (29), (30); the broken line (b) shows the current component discharging from the second parasitic capacitance (32) through the second MOS.multidot.FET (16). In this case, the charge of the second parasitic capacitance (32) is discharged until the substrate potential of the p-type substrate (1) is decreased to the value of the equation (V) as -[V.sub.DD -V.sub.T15 -V.sub.F29 ]. In the normal state, it is -[V.sub.DD -V.sub.T15 -V.sub.F29 ] as shown in FIG. 3(c).
On the other hand, in the case of V.sub.T16 &lt;V.sub.F29 =V.sub.F30, the relation of the discharge current of the second parasitic capacitance (32) through the first and second parasitic diodes (29), (30) shown by the full line (a) in FIG. 4 and the discharge current of the second parasitic capacitance (32) through the second MOS.multidot.FET (16) shown by the broken line (b) in FIG. 4 are reversed. The substrate potential of the p-type substrate (1), in the normal state, is -[V.sub.DD -V.sub.T15 -V.sub.T16 ] as the equation (IV).
Electrons are injected into the p-type substrate (1) when the second parasitic capacitance (32) is discharged through the first and second parasitic diodes (29), (30). A part of the electrons remain in the p-type substrate (1) for a while and then, the electrons disappear by bonding to positive holes as the majority carrier in the p-type substrate (1). The other electrons pass through the second MOS.multidot.FET (16), third wiring line (28) and the sixth electrode (22) to reach the second main surface of the p-type substrate (1), and the electrons disappear by immediately bonding to positive holes at the contact part of the sixth electrode (22) and the second main surface of the p-type substrate (1). The depletion of positive holes corresponding to the electrons is formed in the p-type substrate (1). Therefore, in the conventional substrate bias circuit, the potential of the p-type substrate (1) can be negative. When the substrate bias circuit and a RAM-IC are formed on the same p-type substrate (1), some of electrons injected by the discharged current passed from the second parasitic capacitance (32) through the first and second parasitic diodes (29), (30), remain in the p-type substrate (1) for a while and move in the p-type substrate (1). If the electrons are captured by the memory cell of the RAM-IC, logical data dynamically memorized in the memory cell disappear to cause the erroneous operation of the RAM-IC. This is a fatal disadvantage.
The memory cell of the RAM-IC will be described.
FIG. 5 is a sectional view of the memory cell of the RAM-IC comprising one MOS.multidot.FET and one MOS capacitor. FIG. 6 is an equivalent circuit diagram thereof.
In the drawings, the reference numeral (1) designates a p-type substrate having high specific resistance; (33) and (34) respectively designate n.sup.+ -drain and n.sup.+ -source regions which have low specific resistance and are selectively formed in a specific space on the first main surface of the p-type substrate (1); (35) designates a first gate insulating layer formed from the n.sup.+ -drain region (33) to the n.sup.+ -source region (34) on the main surface of the p-type substrate (1); (36) designates a first gate electrode formed on the first gate insulating layer (35); (37) designates a MOS.multidot.FET comprising the n.sup.+ -drain region (33), the n.sup.+ -source region (34) and the first gate electrode (36); (38) designates a second gate insulating layer which is formed in contact with the n.sup.+ -source region (34) on the first main surface of the p-type substrate (1) at the reverse side to the n.sup.+ -drain region (33); (39) designate a second gate electrode formed on the second gate insulating layer (38); (40) designates a MOS capacitor formed on the first main surface under the second gate electrode (39) and the second gate insulating layer of the p-type substrate (41) designates a bit line as the first wiring line lead out from the n.sup.+ -drain region (33); (42) designates a word line as the second wiring line lead out from the first gate electrode (36); (43) designates the third wiring line lead out from the second gate electrode (39) to which the maximum voltage (such as +5 V) used in the RAM-IC is usually applied.
The operation of the memory cell will be described.
When data having high potential (corresponding to data "1") are written-in the memory cell, high potential is applied to the bit line (41) and then, high potential is applied to the word line (42) whereby the MOS.multidot.FET (37) is turned on to transmit the high potential of the bit line (41) to the n.sup.+ -source region (34) of the MOS.multidot.FET (37)and the MOS capacitor (40) is charged in high potential. In this state, only a small number of electrons remain in the MOS capacitor (40).
When the potential of the word line (42) is lowered to change the MOS.multidot.FET (37) in the OFF state, the bit line (41) is electrically insulated from the n.sup.+ -source region of the MOS.multidot.FET (37) and the MOS capacitor (40) is kept at the high potential. This is the state of memorizing data in the memory cell. In this state, when the substrate bias circuit shown in FIG. 1 is operated, electrons are injected into the p-type substrate (1) through the first and second parasitic diodes (29), (30) as described referring to the equivalent circuit diagram of FIG. 2. The injected electrons are minor carriers in the p-type substrate whereby the electrons usually disappear near the injected source by bonding to positive holes. However, some of electrons reach near the MOS capacitor (40) of the memory cell as designated by the reference E in FIG. 5. Thus, the electrons are captured by the MOS capacitor (40) which is charged in high potential to have only small number of electrons. Therefore, the charge voltage of the MOS capacitor (40) is changed from high voltage to low voltage sometimes to the ground potential. The ground potential corresponds to the data "0". The data written as the data "1" are output as the data "0" are output as the data "0". Thus, the erroneous operation of the RAM-IC is caused. This is the fatal disadvantage.